EU6881Q
- Description
- The high-performance motor drive chip incorporates ME core and 8051 core. ME core integrates FOC,
MDU, LPF, PID and SVPWM modules that allow for automatic calculation of FOC or square-wave control
by the hardware for sensored/sensorless BLDC/PMSM motors, and implements SVPWM control for the two
phase step motor. 8051 core is used for parameter configuration and routine processing. Most of 8051 core
instruction cycle takes 1T or 2T clock cycle(s). The dual cores work in parallel to achieve high-performance
motor control. The chip integrates high-speed operational amplifiers, comparators, high-speed ADC, CRC,
SPI, I2C, UART, LIN and Timers. The LIN module supports auto-addressing for multiple slave devices at
different baud rates, and the built-in MOS driver delivers up to 1A drive current. Also, the chip offers built
in high-voltage LDO, making it suitable for FOC or square-wave based BLDC/PMSM motors and SVPWM
based two-phase step motors.
- Features
-
◼ Power supply:
➢ External power supply 6.5V ~ 20V is connected to VCC pin, and internal LDO supplies VDD5
voltage.
◼ Dual core: 8051 core and ME core
◼ An instruction cycle mostly takes 1 or 2 system clock cycle(s)
◼ 32kB Flash ROM with CRC, self-program and code protection
◼ 256 bytes IRAM and 3.75k bytes XRAM
◼ Protection features, including TSD, OCP and OVP
◼ ME: Core integrating PID module, FOC module, MDU auxiliary computing module and LPF
module
◼ 16 interrupt sources with 4 configurable priority levels
◼ Number of GPIOs: 16
◼ Timer:
➢ Timer1: Timer supporting square wave drive timing control, automatic commutation, adaptive
diode freewheeling masking, cycle-by-cycle current limiting and Hall/BEMF-based position
sensing;
➢ Timer2: Timer supporting PWM output, measurement of duty cycle and period of input PWM
wave, measurement of the time of set PWM wave numbers, QEP decoding, tailwind/headwind
detection (RSD), rotation direction and speed detection of step motor
➢ Timer3/Timer4: Timers supporting PWM output, and measurement of duty cycle and period of
input PWM wave. Timer4 supports FG generation and Timer3 supports up to 40MHz input.
➢ Systick Timer
➢ RTC
◼ Communication interface:
➢ 1*SPI
➢ 1*I²C
➢ 1*UART, supporting single-wire mode
➢ 1*LIN, integrating LIN transceiver to implement single-wire mode, fixed baud rate mode,
automatic baud rate mode and auto-addressing mode
➢ Dual-channel DMA: supporting data transmission via I2C/SPI/UART/LIN
◼ Analogue peripherals:
➢ 12-bit ADC: Internal VREF or external VREF selectable as reference voltage
➢ Number of ADC channels: 11
➢ Internal VREF, with configurable 3V, 4V, 4.5V or VDD5
➢ Zero-crossing point (ZCP) detection circuit
➢ 2-channel analog comparators
➢ DAC: Single-channel 6-bit
◼ Drive Type
➢ Built-in MOSFET, high side + low side = 0.25Ω
➢ Drive current: 1A
◼ FOC module supports single/dual/triple-shunt current sampling
◼ Two-phase step motor controlled by SVPWM and a three-phase inverter, which supports dual
shunt current sampling
◼ System clock
➢ Built-in 20MHz fast RC oscillator
➢ Built-in 32.8kHz slow RC oscillator
◼ WDT
◼ LVD
◼ Temperature sensor
◼ Two-wire FICE protocol based in-circuit emulation
- Package
-
QFN40
- Datasheet
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