ES9650AH
- Description
- ES9650 is an Intelligent Power Module (IPM)that contains dual cores, controller, drive and power devices in a
package. The high-performance motor drive chip incorporates ME core and 8051 core. ME core integrates FOC, MDU,
LPF, PID and SVPWM modules which allow for automatic calculation of FOC or square wave control by hardware
used for sensored/sensorless BLDC motors. 8051 core is used for parameter configuration and routine processing. Most
of 8051 core instruction cycle takes 1 or 2 clock cycle(s). The dual cores work in parallel to achieve high-performance
motor control. The chip integrates high-speed operational amplifiers, comparators, high-speed ADC, CRC, I
2C, UART,
Timers and high-speed LDO, which are essential for FOC or square wave control based BLDC motors.
Package of ES9650 is QHFBP8080-60L.
- Features
-
Features
◼ Power supply:
➢ External power supply 5V ~ 28V is connected to VCC pin, and internal LDO supplies VDD5
voltage
◼ MOSFET:
➢ P-Channel:
◼ VDS = - 40V
◼ ID = - 5A
◼ RDS = 25mΩ
➢ N-Channel:
◼ VDS = 40V
◼ ID = 5A
◼ RDS = 15mΩ
◼ Dual-core: 8051 and ME core
◼ An instruction cycle mostly takes 1 or 2 system clock cycle(s)
◼ 16kB Flash ROM, CRC, self-programming, and code protection
◼ 256 bytes IRAM and 768 bytes XRAM
◼ ME: Core integrating PID module, FOC module, MDU auxiliary computing module and LPF module
◼ 16 interrupt sources with 4 configurable priority levels
◼ GPIO: 25 GPIOs
◼ Timers:
➢ Timer1: Timer supporting square wave drive timing control, automatic commutation, cycle-by-cycle
current limiting and Hall/BEMF-based position sensing;
➢ Timer2: Timer supporting PWM output, measurement of duty cycle and period of input PWM wave,
measurement of the time of set PWM wave numbers, QEP decoding, tailwind/headwind detection
(RSD), rotation direction and speed detection of step motor
➢ Timer3/Timer4: Timers supporting PWM output, and measurement of duty cycle and period of input
PWM wave. Timer4 supports FG generation and Timer3 supports up to 48MHz input.
➢ Systick timer
➢ RTC
◼ Communication interfaces:
➢ 1*I2C
➢ 2*UARTs, supporting single-wire mode
➢ Dual-channel DMA: Support data transmission via I
2C/UART
◼ Analog peripherals:
➢ 12-bit ADC: 1μs conversion time with internal VREF or external VREF as reference voltage
➢ Number of ADC channels: 12
➢ Built-in VREF: VDD5
➢ Built-in VHALF (VREF/2)
➢ 3 standalone operational amplifiers, where AMP0 can be configured as PGA
➢ 3-channel analog comparators
➢ DAC: Single-channel 9-bit, single0channel 6-bit
◼ FOC module supports single/dual/triple-shunt current sampling
◼ Oscillator:
➢ Built-in 24MHz high-speed RC oscillator
➢ Built-in 32.8kHz low-speed RC oscillator
◼ WDT
◼ LVD
◼ TSD
◼ Two-wire FICE protocol based in-circuit emulation
- Package
-
QHFBP8080-60L
- Datasheet
-
Download
