EU6366Q
- Description
- The high-performance motor drive chip incorporates ME core and 8051 core. ME core integrates FOC, MDU,
LPF, PID and SVPWM modules that allow for automatic calculation of FOC or square-wave control by the
hardware for sensored/sensorless BLDC/PMSM motors. 8051 core is used for parameter configuration and routine
processing. Most of 8051 core instruction cycle takes 1T or 2T clock cycle(s). The dual cores work in parallel to
achieve high-performance motor control. The chip integrates high-speed operational amplifiers, comparators,
high-speed ADC, CRC, SPI, I2C, UART, LIN, CAN, Timers, built-in LDO, which are suitable for FOC or square
wave based BLDC/PMSM motors.
- Features
-
◼ Power supply:
➢ High-voltage single-power supply mode: When VCC_MODE = 0, external power supply
6.5V~28V is connected to VCC pin, and internal LDO supplies VDD5 voltage.
◼ Dual core: 8051 core and ME core
◼ An instruction cycle mostly takes 1 or 2 system clock cycle(s)
◼ 32kB Flash ROM with CRC, self-program and code protection
◼ 256 bytes IRAM and 3.75k bytes XRAM
◼ ME: Core integrating PID module, FOC module, MDU auxiliary computing module and LPF module
◼ 16 interrupt sources with 4 configurable priority levels
◼ 31 GPIOs
◼ Timers:
➢ Timer1: Timer supporting square-wave drive timing control, automatic commutation, cycle-by
cycle current limiting and Hall/BEMF-based position sensing
➢ Timer2: Timer supporting PWM output, measurement of duty cycle and period of input PWM
wave, measurement of the time of set PWM wave numbers, QEP decoding, tailwind/headwind
detection, and rotation direction and speed detection of step motor
➢ Timer3/Timer4: Timers supporting PWM output, and measurement of duty cycle and period of
input PWM wave Timer4 supports FG generation and Timer3 supports up to 48MHz input
➢ Systick Timer
➢ RTC
◼ Communication interfaces:
➢ 1*SPI
➢ 1*I2C
➢ 2*UARTs, supporting single-wire mode
➢ 1*LIN, supporting single-wire mode
➢ 1*CAN
➢ Dual-channel DMA: supporting data transmission via I2C/SPI/UART/LIN
◼ Analog peripherals:
➢ 12-bit ADC, operating with 1μs conversion time and internal VREF or external VREF selectable
as reference voltage
➢ Number of ADC channels: 16. Among them, ADC15 is used for internal sampling.
➢ Internal VREF. 3V, 4V, 4.5V and VDD5 can be selected as the internal reference.
➢ Internal VHALF, with VREF/2, 1/4 VREF, 1/8 VREF or 25/64 VREF as the internal reference
➢ Four standalone operational amplifier(s), where PGA is configurable
➢ 3-channel analog comparator
➢ DAC: Single-channel 9-bit, single-channel 6-bit
◼ Driver type
➢ Built-in MOSFET driver: 6N pre-driver output
◼ FOC module supports single/dual/triple-shunt current sampling
◼ System clock
➢ Built-in 24MHz high-speed RC oscillator
➢ Built-in 32.8kHz low-speed RC oscillator
➢ Support external clock input
➢ Support external 32768Hz crystal clock
◼ WDT
◼ LVD
◼ TSD
◼ Two-wire FICE protocol based in-circuit emulation
- Package
-
QFN56
- Datasheet
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